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ds05-20889-1e fujitsu semiconductor data sheet flash memory cmos 32m (2m 16) bit page dual operation mbm29pds322te/be 10/11 n n n n description the mbm29pds322te/be is 32m-bit, 1.8 v-only flash memory organized as 2m words of 16 bits each. the device is offered in 63-ball fbga package. this device is designed to be programmed in system with standard system 1.8 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. the device is organized into two banks, bank 1 and bank 2, which can be considered to be two separate memory arrays as far as certain operations are concerned. this device is the same as fujitsus standard 1.8 v only flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. (continued) n n n n product line-up n n n n pac k ag e part no. mbm29pds322te/be ordering part no. v cc = 2.0 v +0.2 v C0.2 v 10 11 max. random address access time (ns) 100 115 max. page address access time (ns) 45 45 max. ce access time (ns) 100 115 max. oe access time (ns) 35 45 63-ball plastic fbga (bga-63p-m01)
mbm29pds322te/be 10/11 2 (continued) the device provides truly high performance non-volatile flash memory solution. the device offers fast page access times of 45 ns with random access times of 100 ns and 115 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the page size is 4 words. the device is pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the device is programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically time the erase pulse widths and verify proper cell margin. a sector is typically erased and verified in 1.0 second. (if already completely preprogrammed.) the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the device is erased when shipped from the factory. the device features single 1.8 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been completed, the device internally resets to the read mode. the device also has a hardware reset pin. when this pin is driven low, execution of any embedded program algorithm or embedded erase algorithm is terminated. the internal state machine is then reset to the read mode. the reset pin may be tied to the system reset circuitry. therefore, if a system reset occurs during the embedded program algorithm or embedded erase algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. these locations need re-writing after the reset. resetting the device enables the systems microprocessor to read the boot-up firmware from the flash memory. fujitsus flash technology combines years of eprom and e 2 prom experience to produce the highest levels of quality, reliability, and cost effectiveness. the device memory electrically erase the entire chip or all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom programming mechanism of hot electron injection.
mbm29pds322te/be 10/11 3 n n n n features ? 0.23 m m process technology ? simultaneous read/write operations (dual bank) host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. read-while-erase read-while-program ? high performance page mode 45 ns maximum page access time (100 ns random access time) 4 words page size ? single 1.8 v read, program, and erase minimized system level power requirements ? compatible with jedec-standard commands use the same software commands as e 2 proms. ? compatible with jedec-standard world-wide pinouts 63-ball fbga (package suffix: pbt) ? minimum 100,000 program/erase cycles ? sector erase architecture eight 4 kword and sixty-three 32 kword sectors in word mode any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture t = top sector b = bottom sector ? hidden rom (hi-rom) region 64 kbyte of hi-rom, accessible through a new hi-rom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ? wp /acc input pin at v il , allows protection of boot sectors, regardless of sector protection/unprotection status. at v ih , allows removal of boot sector protection. at v acc , increases program performance. ? embedded erase tm algorithms automatically pre-programs and erases the chip or any sector. ? embedded program tm algorithms automatically writes and verifies data at specified address. ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device. ? sector group protection hardware method disables any combination of sector groups from program or erase operations. ? sector group protection set function by extended sector group protection command ? fast programming function by extended command ? temporary sector group unprotection temporary sector group unprotection via the reset pin.
mbm29pds322te/be 10/11 4 table 1: mbm29pds322te/be device bank division device part number organization bank 1 bank 2 megabits sector sizes megabits sector sizes mbm29pds322te/be 16 4 mbit eight 4 kword, seven 32 kword 28 mbit fifty-six 32 kword
mbm29pds322te/be 10/11 5 n n n n pin assignment (top view) (bga-63p-m01) a8 b8 n.c. * n.c. * n.c. * n.c. * a7 b7 c7 d7 e7 f7 g7 h7 j7 k7 c6 d6 e6 f6 g6 h6 j6 k6 a 9 a 8 a 10 a 11 dq 7 dq 14 dq 13 dq 6 c5 d5 e5 f5 g5 h5 j5 k5 we reset n.c. a 19 dq 5 dq 12 v cc dq 4 c4 d4 e4 f4 g4 h4 j4 k4 ry/by wp/acc a 18 a 20 dq 2 dq 10 dq 11 dq 3 c3 d3 e3 f3 g3 h3 j3 k3 a 7 a 17 a 6 a 5 dq 0 dq 8 dq 9 dq 1 c2 d2 e2 f2 g2 h2 j2 k2 l2 m2 a 3 a2 n.c. * a1 n.c. * b1 n.c. * a 4 a 2 a 1 a 0 ce oe v ss l7 l8 m7 a 13 a 12 a 14 a 15 a 16 dq 15 v ss n.c. * n.c. * m8 n.c. * n.c. * l1 n.c. * m1 n.c. * n.c. * n.c. * n.c. (marking side) *: peripheral balls on each corner are shorted together via the substrate but not connected to the die.
mbm29pds322te/be 10/11 6 n n n n pin description table 2: mbm29pds322te/be pin configuration pin name function a 20 to a 0 address inputs dq 15 to dq 0 data inputs/outputs ce chip enable oe output enable we write enable ry/by ready/busy output reset hardware reset pin/temporary sector group unprotection wp /acc hardware write protection/program acceleration n.c. no internal connection v ss device ground v cc device power supply
mbm29pds322te/be 10/11 7 n n n n block diagram n n n n logic symbol v cc v ss a 20 to a 0 reset we ce oe wp/acc dq 15 to dq 0 dq 15 to dq 0 bank 2 address bank 1 address state control & command register status ry/by control cell matrix (bank 2) x-decoder y-gating cell matrix (bank 1) x-decoder y-gating 21 a 20 to a 0 we oe ce dq 15 to dq 0 16 wa/acc reset ry/by
mbm29pds322te/be 10/11 8 n n n n device bus operation table 3: mbm29pds322te/be user bus operations legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see dc characteristics for voltage levels. *1: manufacturer and device codes may also be accessed via a command register write sequence. see table 3. *2: refer to section on sector group protection. *3: we can be v il if oe is v il , oe at v ih initiates the write operations. *4: v cc must be between the minimum and maximum of the operation range. *5: it is also used for the extended sector group protection. *6: protect outermost 2 4 kwords of the boot block sectors. operation ce oe we a 0 a 1 a 2 a 3 a 6 a 9 dq 15 to dq 0 reset wp / acc auto-select manufacturer code * 1 llhlllllv id code h x auto-select device code * 1 llhhllllv id code h x extended auto-select device code * 1 l lhl/hhhhlv id code h x read * 3 llha 0 a 1 a 2 a 3 a 6 a 9 d out hx standby h x xxxxxxx high-z h x output disable lhhxxxxxx high-z h x write (program/erase) l h l a 0 a 1 a 2 a 3 a 6 a 9 d in hx enable sector group protection * 2, * 4 lv id lhlllv id xhx verify sector group protection * 2, * 4 llhlhlllv id code h x temporary sector group unprotection * 5 xxxxxxxxx x v id x reset (hardware) / standby xxxxxxxxx high-z l x boot block sector write protection * 6 xxxxxxxxx x x l
mbm29pds322te/be 10/11 9 table 4: mbm29pds322te/be command definitions *1: this command is valid while fast mode. *2: this command is valid while reset = v id . *3: this command is valid while hi-rom mode. *4: the data 00h is also acceptable. note 1.address bits a 20 to a 12 = x = h or l for all address commands except or program address (pa), sector address (sa), and bank address (ba). 2.bus operations are defined in table 8. 3.ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset word 1 xxxh f0h read/reset word 3 555h aah 2aah 55h 555h f0h ra rd auto select word 3 555h aah 2aah 55h (ba) 555h 90h program word 4 555h aah 2aah 55h 555h a0h pa pd chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h erase suspend 1 ba b0h erase resume 1 ba30h set to fast mode word 3 555h aah 2aah 55h 555h 20h fast program * 1 word 2 xxxh a0h pa pd reset from fast mode * 1 word 2 ba 90h xxxh * 4 f0h extended sector group protection * 2 word 4 xxxh 60h spa 60h spa 40h spa sd query word 1 (ba) 55h 98h hi-rom entry word 3 555h aah 2aah 55h 555h 88h hi-rom program * 3 word 4 555h aah 2aah 55h 555h a0h (hra) pa pd hi-rom erase * 3 word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h hra 30h hi-rom exit * 3 word 4 555h aah 2aah 55h (hrba) 555h 90h xxxh 00h
mbm29pds322te/be 10/11 10 sa = address of the sector to be erased. the combination of a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address (a 20 to a 15 ) 4.rd = data read from location ra during the read operation. pd = data to be programmed at location pa. data is latched on the falling edge of write pulse. 5.spa = sector group address to be protected. set sector group address (sga) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. 6.hra = address of the hi-rom area 29pds322te (top boot type)word mode:1f8000h to 1fffffh 29pds322be (bottom boot type)word mode:000000h to 007fffh 7.hrba =bank address of the hi-rom area 29pds322te (top boot type):a 20 = a 19 = a 18 = a 17 = a 16 = a 15 = 1 29pds322be (bottom boot type):a 20 = a 19 = a 18 = a 17 = a 16 = a 15 = 0 8.the system should generate the following address patterns: word mode: 555h or 2aah to addresses a 10 to a 0 9.both read/reset commands are functionally equivalent, resetting the device to the read mode.
mbm29pds322te/be 10/11 11 table 5.1 mbm29pds322te sector group protection verify autoselect codes *1:outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2:when v id is applied, both bank 1 and bank 2 become autoselect mode, which leads to the simultaneous operation unable to be executed. consequently, specifying the bank address is not demanded. however, the bank address needs to be indicated when autoselect mode is read out at command mode; because then it becomes ok to activate simultaneous operation. *3:a read cycle at address (ba)01h outputs device code. when 227eh was output, this indicates that there will require two additional codes, called extended device codes. therefore, the system may continue reading out these extended device codes at the address of (ba)0eh, as well as at (ba)0fh. table 5.2 expanded autoselect code table (w): word mode type a 20 to a 12 a 6 a 3 a 2 a 1 a 0 code (hex) manufactures code ba *2 v il v il v il v il v il 04h device code word ba *2 v il v il v il v il v ih 227eh extended device code * 3 word ba *2 v il v ih v ih v ih v il 2206h word ba *2 v il v ih v ih v ih v ih 2201h sector group protection sector group addresses v il v il v il v ih v il 01h *1 type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h 0 0 0 0 0 0 0000000100 device code (w) 227eh 0 0 1 0 0 0 1001111110 extended device code (w) 2206h 0 0 1 0 0 0 1000000110 (w) 2201h 0 0 1 0 0 0 1000000001 sector group protection 01h 0 0 0 0 0 0 0000000001
mbm29pds322te/be 10/11 12 table 5.3 mbm29pds322be sector group protection verify autoselect codes *1:outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2:when v id is applied, both bank 1 and bank 2 become autoselect mode, which leads to the simultaneous operation unable to be executed. consequently, specifying the bank address is not demanded. however, the bank address needs to be indicated when autoselect mode is read out at command mode; because then it becomes ok to activate simultaneous operation. * 3:a read cycle at address (ba)01h outputs device code. when 227eh was output, this indicates that there will require two additional codes, called extended device codes. therefore, the system may continue reading out these extended device codes at the address of (ba)0eh, as well as at (ba)0fh. table 5.4 expanded autoselect code table (w): word mode type a 20 to a 12 a 6 a 3 a 2 a 1 a 0 code (hex) manufactures code ba *2 v il v il v il v il v il 04h device code word ba *2 v il v il v il v il v ih 227eh extended device code * 3 word ba *2 v il v ih v ih v ih v il 2206h word ba *2 v il v ih v ih v ih v ih 2200h sector group protection sector group addresses v il v il v il v ih v il 01h *1 type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h0000000000000100 device code (w) 227eh 0010001001111110 extended device code (w) 2206h 0010001000000110 (w) 2200h 0010001000000000 sector group protection 01h0000000000000001
mbm29pds322te/be 10/11 13 n n n n flexible sector-erase architecture table 6.1 sector address tables (mbm29pds322te) (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 14 a 13 a 12 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa0 0 0 0 0 0 0 x x x 32 000000h to 007fffh sa1 0 0 0 0 0 1 x x x 32 008000h to 00ffffh sa2 0 0 0 0 1 0 x x x 32 010000h to 017fffh sa3 0 0 0 0 1 1 x x x 32 018000h to 01ffffh sa4 0 0 0 1 0 0 x x x 32 020000h to 027fffh sa5 0 0 0 1 0 1 x x x 32 028000h to 02ffffh sa6 0 0 0 1 1 0 x x x 32 030000h to 037fffh sa7 0 0 0 1 1 1 x x x 32 038000h to 03ffffh sa8 0 0 1 0 0 0 x x x 32 040000h to 047fffh sa9 0 0 1 0 0 1 x x x 32 048000h to 04ffffh sa10 0 0 1 0 1 0 x x x 32 050000h to 057fffh sa11 0 0 1 0 1 1 x x x 32 058000h to 05ffffh sa12 0 0 1 1 0 0 x x x 32 060000h to 067fffh sa13 0 0 1 1 0 1 x x x 32 068000h to 06ffffh sa14 0 0 1 1 1 0 x x x 32 070000h to 077fffh sa15 0 0 1 1 1 1 x x x 32 078000h to 07ffffh sa16 0 1 0 0 0 0 x x x 32 080000h to 087fffh sa17 0 1 0 0 0 1 x x x 32 088000h to 08ffffh sa18 0 1 0 0 1 0 x x x 32 090000h to 097fffh sa19 0 1 0 0 1 1 x x x 32 098000h to 09ffffh sa20 0 1 0 1 0 0 x x x 32 0a0000h to 0a7fffh sa21 0 1 0 1 0 1 x x x 32 0a8000h to 0affffh sa22 0 1 0 1 1 0 x x x 32 0b0000h to 0b7fffh sa23 0 1 0 1 1 1 x x x 32 0b8000h to 0bffffh sa24 0 1 1 0 0 0 x x x 32 0c0000h to 0c7fffh sa25 0 1 1 0 0 1 x x x 32 0c8000h to 0cffffh sa26 0 1 1 0 1 0 x x x 32 0d0000h to 0d7fffh sa27 0 1 1 0 1 1 x x x 32 0d8000h to 0dffffh sa28 0 1 1 1 0 0 x x x 32 0e0000h to 0e7fffh sa29 0 1 1 1 0 1 x x x 32 0e8000h to 0effffh sa30 0 1 1 1 1 0 x x x 32 0f0000h to 0f7fffh sa31 0 1 1 1 1 1 x x x 32 0f8000h to 0fffffh sa32 1 0 0 0 0 0 x x x 32 100000h to 107fffh sa33 1 0 0 0 0 1 x x x 32 108000h to 10ffffh sa34 1 0 0 0 1 0 x x x 32 110000h to 117fffh
mbm29pds322te/be 10/11 14 (continued) mbm29pds322te top boot sector architecture bank sector sector address sector size (kwords) ( 16) address range bank address a 14 a 13 a 12 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa35 1 0 0 0 1 1 x x x 32 118000h to 11ffffh sa36 1 0 0 1 0 0 x x x 32 120000h to 127fffh sa37 1 0 0 1 0 1 x x x 32 128000h to 12ffffh sa38 1 0 0 1 1 0 x x x 32 130000h to 137fffh sa39 1 0 0 1 1 1 x x x 32 138000h to 13ffffh sa40 1 0 1 0 0 0 x x x 32 140000h to 147fffh sa41 1 0 1 0 0 1 x x x 32 148000h to 14ffffh sa42 1 0 1 0 1 0 x x x 32 150000h to 157fffh sa43 1 0 1 0 1 1 x x x 32 158000h to 15ffffh sa44 1 0 1 1 0 0 x x x 32 160000h to 167fffh sa45 1 0 1 1 0 1 x x x 32 168000h to 16ffffh sa46 1 0 1 1 1 0 x x x 32 170000h to 177fffh sa47 1 0 1 1 1 1 x x x 32 178000h to 17ffffh sa48 1 1 0 0 0 0 x x x 32 180000h to 187fffh sa49 1 1 0 0 0 1 x x x 32 188000h to 18ffffh sa50 1 1 0 0 1 0 x x x 32 190000h to 197fffh sa51 1 1 0 0 1 1 x x x 32 198000h to 19ffffh sa52 1 1 0 1 0 0 x x x 32 1a0000h to 1a7fffh sa53 1 1 0 1 0 1 x x x 32 1a8000h to 1affffh sa54 1 1 0 1 1 0 x x x 32 1b0000h to 1b7fffh sa55 1 1 0 1 1 1 x x x 32 1b8000h to 1bffffh bank 1 sa56 1 1 1 0 0 0 x x x 32 1c0000h to 1c7fffh sa57 1 1 1 0 0 1 x x x 32 1c8000h to 1cffffh sa58 1 1 1 0 1 0 x x x 32 1d0000h to 1d7fffh sa59 1 1 1 0 1 1 x x x 32 1d8000h to 1dffffh sa60 1 1 1 1 0 0 x x x 32 1e0000h to 1e7fffh sa61 1 1 1 1 0 1 x x x 32 1e8000h to 1effffh sa62 1 1 1 1 1 0 x x x 32 1f0000h to 1f7fffh sa63 1 1 1 1 1 1 0 0 0 4 1f8000h to 1f8fffh sa64 1 1 1 1 1 1 0 0 1 4 1f9000h to 1f9fffh sa65111111010 4 1fa000h to 1fafffh sa66111111011 4 1fb000h to 1fbfffh sa67111111100 4 1fc000h to 1fcfffh sa68111111101 4 1fd000h to 1fdfffh sa69111111110 4 1fe000h to 1fefffh sa70111111111 4 1ff000h to 1fffffh
mbm29pds322te/be 10/11 15 table 6.2 sector address tables (mbm29pds322be) (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 14 a 13 a 12 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa70 1 1 1 1 1 1 x x x 32 1f8000h to 1fffffh sa69 1 1 1 1 1 0 x x x 32 1f0000h to 1f7fffh sa68 1 1 1 1 0 1 x x x 32 1e8000h to 1effffh sa67 1 1 1 1 0 0 x x x 32 1e0000h to 1e7fffh sa66 1 1 1 0 1 1 x x x 32 1d8000h to 1dffffh sa65 1 1 1 0 1 0 x x x 32 1d0000h to 1d7fffh sa64 1 1 1 0 0 1 x x x 32 1c8000h to 1cffffh sa63 1 1 1 0 0 0 x x x 32 1c0000h to 1c7fffh sa62 1 1 0 1 1 1 x x x 32 1b8000h to 1bffffh sa61 1 1 0 1 1 0 x x x 32 1b0000h to 1b7fffh sa60 1 1 0 1 0 1 x x x 32 1a8000h to 1affffh sa59 1 1 0 1 0 0 x x x 32 1a0000h to 1a7fffh sa58 1 1 0 0 1 1 x x x 32 198000h to 19ffffh sa57 1 1 0 0 1 0 x x x 32 190000h to 197fffh sa56 1 1 0 0 0 1 x x x 32 188000h to 18ffffh sa55 1 1 0 0 0 0 x x x 32 180000h to 187fffh sa54 1 0 1 1 1 1 x x x 32 178000h to 17ffffh sa53 1 0 1 1 1 0 x x x 32 170000h to 177fffh sa52 1 0 1 1 0 1 x x x 32 168000h to 16ffffh sa51 1 0 1 1 0 0 x x x 32 160000h to 167fffh sa50 1 0 1 0 1 1 x x x 32 158000h to 15ffffh sa49 1 0 1 0 1 0 x x x 32 150000h to 157fffh sa48 1 0 1 0 0 1 x x x 32 148000h to 14ffffh sa47 1 0 1 0 0 0 x x x 32 140000h to 147fffh sa46 1 0 0 1 1 1 x x x 32 138000h to 13ffffh sa45 1 0 0 1 1 0 x x x 32 130000h to 137fffh sa44 1 0 0 1 0 1 x x x 32 128000h to 12ffffh sa43 1 0 0 1 0 0 x x x 32 120000h to 127fffh sa42 1 0 0 0 1 1 x x x 32 118000h to 11ffffh sa41 1 0 0 0 1 0 x x x 32 110000h to 117fffh sa40 1 0 0 0 0 1 x x x 32 108000h to 10ffffh sa39 1 0 0 0 0 0 x x x 32 100000h to 107fffh sa38 0 1 1 1 1 1 x x x 32 0f8000h to 0fffffh sa37 0 1 1 1 1 0 x x x 32 0f0000h to 0f7fffh sa36 0 1 1 1 0 1 x x x 32 0e8000h to 0effffh sa35 0 1 1 1 0 0 x x x 32 0e0000h to 0e7fffh
mbm29pds322te/be 10/11 16 (continued) mbm29pds322be bottom boot sector architecture bank sector sector address sector size (kwords) ( 16) address range bank address a 14 a 13 a 12 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa34 0 1 1 0 1 1 x x x 32 0d8000h to 0dffffh sa33 0 1 1 0 1 0 x x x 32 0d0000h to 0d7fffh sa32 0 1 1 0 0 1 x x x 32 0c8000h to 0cffffh sa31 0 1 1 0 0 0 x x x 32 0c0000h to 0c7fffh sa30 0 1 0 1 1 1 x x x 32 0b8000h to 0bffffh sa29 0 1 0 1 1 0 x x x 32 0b0000h to 0b7fffh sa28 0 1 0 1 0 1 x x x 32 0a8000h to 0affffh sa27 0 1 0 1 0 0 x x x 32 0a0000h to 0a7fffh sa26 0 1 0 0 1 1 x x x 32 098000h to 09ffffh sa25 0 1 0 0 1 0 x x x 32 090000h to 097fffh sa24 0 1 0 0 0 1 x x x 32 088000h to 08ffffh sa23 0 1 0 0 0 0 x x x 32 080000h to 087fffh sa22 0 0 1 1 1 1 x x x 32 078000h to 07ffffh sa21 0 0 1 1 1 0 x x x 32 070000h to 077fffh sa20 0 0 1 1 0 1 x x x 32 068000h to 06ffffh sa19 0 0 1 1 0 0 x x x 32 060000h to 067fffh sa18 0 0 1 0 1 1 x x x 32 058000h to 05ffffh sa17 0 0 1 0 1 0 x x x 32 050000h to 057fffh sa16 0 0 1 0 0 1 x x x 32 048000h to 04ffffh sa15 0 0 1 0 0 0 x x x 32 040000h to 047fffh bank 1 sa14 0 0 0 1 1 1 x x x 32 038000h to 03ffffh sa13 0 0 0 1 1 0 x x x 32 030000h to 037fffh sa12 0 0 0 1 0 1 x x x 32 028000h to 02ffffh sa11 0 0 0 1 0 0 x x x 32 020000h to 027fffh sa10 0 0 0 0 1 1 x x x 32 018000h to 01ffffh sa9 0 0 0 0 1 0 x x x 32 010000h to 017fffh sa8 0 0 0 0 0 1 x x x 32 008000h to 00ffffh sa7 0 0 0 0 0 0 1 1 1 4 007000h to 007fffh sa6 0 0 0 0 0 0 1 1 0 4 006000h to 006fffh sa5 0 0 0 0 0 0 1 0 1 4 005000h to 005fffh sa4 0 0 0 0 0 0 1 0 0 4 004000h to 004fffh sa3 0 0 0 0 0 0 0 1 1 4 003000h to 003fffh sa2 0 0 0 0 0 0 0 1 0 4 002000h to 002fffh sa1 0 0 0 0 0 0 0 0 1 4 001000h to 001fffh sa0 0 0 0 0 0 0 0 0 0 4 000000h to 000fffh
mbm29pds322te/be 10/11 17 table 7.1 sector group address table (mbm29pds322te) (top boot block) sector group a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 000000xxx sa0 sga1 0000 01 xxx sa1 to sa3 10 11 sga2 0 0 0 1xxxxx sa4 to sa7 sga3 0 0 1 0xxxxxsa8 to sa11 sga4 0 0 1 1xxxxxsa12 to sa15 sga5 0 1 0 0xxxxxsa16 to sa19 sga6 0 1 0 1xxxxxsa20 to sa23 sga7 0 1 1 0xxxxxsa24 to sa27 sga8 0 1 1 1xxxxxsa28 to sa31 sga9 1 0 0 0xxxxxsa32 to sa35 sga10 1 0 0 1xxxxxsa36 to sa39 sga11 1 0 1 0xxxxxsa40 to sa43 sga12 1 0 1 1xxxxxsa44 to sa47 sga13 1 1 0 0xxxxxsa48 to sa51 sga14 1 1 0 1xxxxxsa52 to sa55 sga15 1 1 1 0xxxxxsa56 to sa59 sga16 1 1 1 1 00 x x x sa60 to sa62 01 10 sga17 111111000 sa63 sga18 111111001 sa64 sga19 111111010 sa65 sga20 111111011 sa66 sga21 111111100 sa67 sga22 111111101 sa68 sga23 111111110 sa69 sga24 111111111 sa70
mbm29pds322te/be 10/11 18 table 7.2 sector group address table (mbm29pds322be) (bottom boot block) sector group a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 000000000 sa0 sga1 000000001 sa1 sga2 000000010 sa2 sga3 000000011 sa3 sga4 000000100 sa4 sga5 000000101 sa5 sga6 000000110 sa6 sga7 000000111 sa7 sga8 0000 01 x x x sa8 to sa10 10 11 sga9 0 0 0 1xxxxxsa11 to sa14 sga10 0 0 1 0xxxxxsa15 to sa18 sga11 0 0 1 1xxxxxsa19 to sa22 sga12 0 1 0 0xxxxxsa23 to sa26 sga13 0 1 0 1xxxxxsa27 to sa30 sga14 0 1 1 0xxxxxsa31 to sa34 sga15 0 1 1 1xxxxxsa35 to sa38 sga16 1 0 0 0xxxxxsa39 to sa42 sga17 1 0 0 1xxxxxsa43 to sa46 sga18 1 0 1 0xxxxxsa47 to sa50 sga19 1 0 1 1xxxxxsa51 to sa54 sga20 1 1 0 0xxxxxsa55 to sa58 sga21 1 1 0 1xxxxxsa59 to sa62 sga22 1 1 1 0xxxxxsa63 to sa66 sga23 1 1 1 1 00 x x x sa67 to sa69 01 10 sga24 111111xxx sa70
mbm29pds322te/be 10/11 19 n n n n functional description simultaneous operation the device has feature, which is capable of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional features (read, program, erase, erase-suspend read, and erase-suspend program). the bank selection can be selected by bank address (a 20 to a 15 ) with zero latency. the device has two banks which contain bank 1 (4 kw eight sectors, 32 kw seven sectors) and bank 2 (32 kw fifty-six sectors). the simultaneous operation can not execute multi-function mode in the same bank. table 8 shows the possible combinations for simultaneous operation. (refer to figure 12 back-to-back read/write timing diagram.) table 8 simultaneous operation *: an erase operation may also be suspended to read from or program to a sector not being erased. read mode the device has two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used as the gate data to the output pins if a device is selected. address access time (t acc ) is equal to delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time (t oe ) is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc -t oe time.) when reading out data without changing addresses after power-up, it is necessary to input hardware reset or to change ce pin from h or l. page mode read the device is capable of fast page mode read operation. this mode provides faster read access speed for random locations within a page. the page size of the device is 4 words, within the appropriate page being selected by the higher address bits a 20 to a 2 and the lsb bits a 1 and a 0 within that page. this is an asynchronous operation with the microprocessor supplying the specific word location. the random or initial page access is equal to t acc and subsequent page read access (as long as the locations specified by the microprocessor fall within that page) is equivalent to t pa c c . here again, ce selects the device and oe is the output control and should be used to gate data to the output pins if the device is selected. fast page mode accesses are obtained by keeping a 20 to a 2 constant and changing a 1 and a 0 to select the specific word, within that page. see figure 5.4 for timing specifications. case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode * 5 autoselect mode read mode 6 program mode read mode 7 erase mode * read mode
mbm29pds322te/be 10/11 20 standby mode there are two ways to implement the standby mode on the device, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition, the current consumed is less than 5 m a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l). under this condition the current consumed is less than 5 m a max. once the reset pin is taken high, the device requires t rh as wake up time for outputs to be valid for read access. in the standby mode, the outputs are in the high impedance state, independently of the oe input. automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of the device data. this mode can be useful in the application such as a handy terminal which requires low power consumption. to activate this mode, the device automatically switches themselves to low power mode when the device ad- dresses remain stable during access time of 150 ns. it is not necessary to control ce , we , and oe on the mode. under the mode, the current consumed is typically 50 m a (cmos level). during simultaneous operation, v cc active current (i cc2 ) is required. since the data are latched during this mode, the data are read-out continuously. if the addresses are changed, the mode is canceled automatically, and the device reads the data for changed addresses. output disable with the oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (10.0 v to 11.0 v) on address pin a 9 . two identifier bytes may then be sequenced from the device outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 6 , a 3 , a 2 , a 1 , and a 0 . (see table 3.) the manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in table 4. (refer to autoselect command section.) in the command autoselect mode, the bank addresses ba; (a 20 to a 12 ) must point to a specific bank during the third write bus cycle of the autoselect command. then the autoselect data will be read from that bank while array data can be read from the other bank. a read cycle from address (ba)00h returns the manufacturers code (fujitsu = 04h). and a read cycle from address (ba)01h, (ba)0eh to (ba)0fh returns the device code. (see tables 5.1 to 5.4.) in case of applying v id on a 9 , since both bank 1 and bank 2 enter autoselect mode, the simultaneous operation can not be executed.
mbm29pds322te/be 10/11 21 write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the com- mand register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector group protection the device features hardware sector group protection. this feature will disable both program and erase opera- tions in any combination of twenty five sector groups of memory. (see table 7.) the sector group protection feature is enabled using programming equipment at the users site. the device is shipped with all sector groups unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v), ce = v il and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0). the sector group addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. tables 6.1 and 6.2 define the sector address for each of the seventy one (71) individual sectors, and tables 7.1 and 7.2 define the sector group address for each of the twenty five (25) individual group sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector group addresses must be held constant during the we pulse. see figures 16 and 24 for sector group protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector group addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the device will produce 0 for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , a 2 , a 3 , and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. it is also possible to determine if a sector group is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) are the desired sector group address will produce a logical 1 at dq 0 for a protected sector group. see tables 5.1 to 5.4 for autoselect codes. temporary sector group unprotection this feature allows temporary unprotection of previously protected sector groups of the device in order to change data. the sector group unprotection mode is activated by setting the reset pin to high voltage (v id ). during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group ad- dresses. once the v id is taken away from the reset pin, all the previously protected sector groups will be protected again. refer to figures 17 and 25. extended sector group protection in addition to normal sector group protection, the device has extended sector group protection as extended function. this function enables to protect sector group by forcing v id on reset pin and write a command sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector group protection in this mode. the extended sector group protection requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then, the sector group addresses pins (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (recommend to set v il for the other addresses pins), and write extended sector group protection command (60h). a sector group is
mbm29pds322te/be 10/11 22 typically protected in 250 m s. to verify programming of the protection circuitry, the sector group addresses pins (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) should be set and write a command (40h). following the command write, a logical 1 at device output dq 0 will produce for protected sector in the read operation. if the output is logical 0, please repeat to write extended sector group protection command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih . (refer to the figures 18 and 26.) reset hardware reset the device may be reset by driving the reset pin to v il . the reset pin vs. a pulse requirement and has to be kept low (v il ) for at least t rp in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode t ready after the reset pin is driven low. furthermore, once the reset pin goes high, the device requires an additional t rh before it will allow read access. when the reset pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see figure 14 for the timing diagram. refer to temporary sector group unprotection for additional functionality. boot block sector protection the write protection function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp /acc pin. if the system asserts v il on the wp /acc pin, the device disables program and erase functions in the two outermost 4k word boot sectors independently of whether those sectors are protected or unprotected using the method described in sector protection/unprotection. the two outermost 4k word boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-congfigured device. (mbm29pds322te: sa69 and sa70, mbm29pds322be: sa0 and sa1) if the system asserts v ih on the wp /acc pin, the device reverts to whether the two outermost 4k word boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in sector protection/unprotection. accelerated program operation the device offers accelerated program operation which enables the programming in high speed. if the system asserts v acc to the wp /acc pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. this function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. the system would use a fast program command sequence when programming during acceleration mode. set command to fast mode and reset command from fast mode are not necessary. when the device enters the acceleration mode, the device automatically set to fast mode. therefore, the present sequence could be used for programming and detection of completion during acceleration mode. removing v acc from the wp /acc pin returns the device to normal operation. do not remove v acc from wp / acc pin while programming. see figure 19.
mbm29pds322te/be 10/11 23 n n n n command definitions the device operations are selected by writing specific address and data sequences into the command register. some commands require bank address (ba) input. when command sequences are inputted to bank being read, the commands have priority over reading. table 4 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover, both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, the read/ reset operation is initiated by writing the read/reset command sequence into the command register. micro- processor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read character- istics and waveforms for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the device resides in the target system. prom pro- grammers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autoselect command sequence into the command register. the autoselect command sequence is initiated by firstly writing two unlock cycles. this is followed by a third write cycle that contains the bank address (ba) and the autoselect command. then the manufacture and device codes can be read from the bank, and actual data of memory cell can be read from the another bank. following the command write, a read cycle from address (ba)00h retrieves the manufacture code of 04h. a read cycle at address (ba)01h returns 7eh to indicate that this device uses extended device code. the successive read cycle from (ba)0eh to (ba)0fh returns this extended device code for this device. (see tables 5.1 to 5.4.) the sector state (protection or unprotection) will be informed by address (ba)02h. scanning the sector group addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector group. the programming verification should be performed by verify sector group protection on the protected sector. (see table 3.) the manufacture and device codes can be allowed to read from selected bank. to read the manufacture and device codes and sector protection status from non-selected bank, it is necessary to write read/reset command sequence into the register and then autoselect command should be written into the bank to be read. if the software (program code) for autoselect command is stored into the flash memory, the device and manu- facture codes should be read from the other bank which doesnt contain the software. to terminate the operation, it is necessary to write the read/reset command sequence into the register. to execute the autoselect command during the operation, writing read/reset command sequence must precede the autoselect command.
mbm29pds322te/be 10/11 24 word programming the device is programmed on a word-by-word basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the system can determine the status of the program operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the data polling and toggle bit must be performed at the memory location which is being programmed. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched. (see table 9, hardware sequence flags.) therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed. if hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. figure 20 illustrates the embedded program tm algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (preprogram function). the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the chip erase begins on the rising edge of the last ce or we , whichever happens first in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read the mode. chip erase time; sector erase time all sectors + chip program time (preprogramming) figure 21 illustrates the embedded erase tm algorithm using typical command strings and bus operations.
mbm29pds322te/be 10/11 25 sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of ce or we whichever happens later, while the command (data = 30h) is latched on the rising edge of ce or we which happens first. after time-out of t tow from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations on table4. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than t tow otherwise that command will not be accepted and erasure will not start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of t tow from the rising edge of last ce or we whichever happens first will initiate the execution of the sector erase command(s). if another falling edge of ce or we , whichever happens first occurs within the t tow time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer.) resetting the device once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 70). sector erase does not require the user to program the device prior to erase. the device automatically program all memory locations in the sector(s) to be erased prior to electrical erase (preprogram function). when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the sector erase begins after the t tow time out from the rising edge of ce or we whichever happens first for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to the read mode. data polling and toggle bit must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector erase time + sector program time (preprogramming)] number of sector erase in case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not perform. figure 21 illustrates the embedded erase tm algorithm using typical command strings and bus operations.
mbm29pds322te/be 10/11 26 erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. writing the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command (30h) resumes the erase operation. the bank addresses of sector being erased or erase-suspended should be set when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a maximum of t spd to suspend the erase operation. when the device has entered the erase-suspended mode, the ry/by output pin will be at hi-z and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for program. this program mode is known as the erase-suspend-program mode. again, pro- gramming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase-suspended program operation is detected by the ry/by output pin, data polling of dq 7 or by the toggle bit i (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address within bank being erase-suspended. to resume the operation of sector erase, the resume command (30h) should be written to the bank being erase suspended. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. extended command (1) fast mode the device has fast mode function. this mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, it is necessary to write fast mode reset command into the command register. the first cycle must contain the bank address. (refer to the figure 27.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). (refer to the figure 27.)
mbm29pds322te/be 10/11 27 hidden rom (hi-rom) region the hi-rom feature provides a flash memory region that the system may access through a new command sequence. this is primarily intended for customers who wish to use an electronic serial number (esn) in the device with the esn protected against modification. once the hi-rom region is protected, any further modifi- cation of that region is impossible. this ensures the security of the esn once the product is shipped to the field. the hi-rom region is 32 kwords in length and is stored at the same address as the 4 kw 8 sectors. the mbm29pds322te occupies the address of the word mode 1f8000h to 1fffffh and the mbm29pds322be type occupies the address of the word mode 000000h to 007fffh. after the system has written the enter hi- rom command sequence, the system may read the hi-rom region by using the addresses normally occupied by the boot sectors. that is, the device sends all commands that would normally be sent to the boot sectors to the hi-rom region. this mode of operation continues until the system issues the exit hi-rom command se- quence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. when reading the hi-rom region, either change addresses or change ce pin from h to l. the same procedure should be taken (changing addresses or ce pin from h to l) after the system issues the exit hi-rom command sequence to read actual data of memory cell. hidden rom (hi-rom) entry command the device has a hidden rom area with one time protect function. this area is to enter the security code and to unable the change of the code once set. program/erase is possible in this area until it is protected. however, once it is protected, it is impossible to unprotect, so please use this with caution. hidden rom area is 32 k words and in the same address area as 4 kw sector. the address of top boot is 1f8000h to 1fffffh at word mode and the bottom boot is 000000h to 007fffh at word mode. these areas are normally the boot block area (4 kw 8 sector). therefore, write the hidden rom entry command sequence to enter the hidden rom area. it is called hidden rom mode when the hidden rom area appears. sector other than the boot block area could be read during hidden rom mode. read/program/erase of the hidden rom area is possible during hidden rom mode. write the hidden rom reset command sequence to exit the hidden rom mode. the bank address of the hidden rom should be set on the third cycle of this reset command sequence. hidden rom (hi-rom) program command to program the data to the hidden rom area, write the hidden rom program command sequence during hidden rom mode. this command is the same as the program command in usual except to write the command during hidden rom mode. therefore the detection of completion method is the same as in the past, using the dq 7 data poling, dq 6 toggle bit and ry/by pin. it is necessary to pay attention to the address to be programmed. if the address other than the hidden rom area is selected to program, data of the address will be changed. hidden rom (hi-rom) erase command to erase the hidden rom area, write the hidden rom erase command sequence during hidden rom mode. this command is same as the sector erase command in the past except to write the command during hidden rom mode. therefore the detection of completion method is the same as in the past, using the dq 7 data poling, dq 6 toggle bit and ry/by pin. it is necessary to pay attention to the sector address to be erased. if the sector address other than the hidden rom area is selected, the data of the sector will be changed.
mbm29pds322te/be 10/11 28 hidden rom (hi-rom) protect command there are two methods to protect the hidden rom area. one is to write the sector group protect setup com- mand(60h), set the sector address in the hidden rom area and (a 6 , a 3 , a 2 ,a 1 , a 0 ) = (0,0,0,1,0), and write the sector group protect command(60h) during the hidden rom mode. the same command sequence could be used because, it is the same as the extension sector group protect in the past except that it is in the hidden rom mode and it does not apply high voltage to reset pin. please refer to function explanation extended sector group protection for details of extension sector group protect setting. the other is to apply high voltage (v id ) to a 9 and oe , set the sector address in the hidden rom area and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0), and apply the write pulse during the hidden rom mode. to verify the protect circuit, apply high voltage (v id ) to a 9 , specify (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) and the sector address in the hidden rom area, and read. when 1 appears on dq 0 , the protect setting is completed. 0 will appear on dq 0 if it is not protected. please apply write pulse again. the same command sequence could be used for the above method because other than the hidden rom mode, it is the same as the sector group protect previously mentioned. please refer to function explanation sector group protection for details of the sector group protect setting. other sector group will be effected if the address other than those for hidden rom area is selected for the sector group address, so please be careful. once it is protected, protection can not be cancelled, so please pay the closest attention. write operation status detailed in table 9 are all the status flags that can determine the status of the bank for the current mode operation. the read operation from the bank which doesnt operate embedded algorithm returns data of memory cells. these bits offer a method for determining whether a embedded algorithm is completed properly. the information on dq 2 is address sensitive. this means that if an address from an erasing sector is consecutively read, then the dq 2 bit will toggle. however, dq 2 will not toggle if an address from a non-erasing sector is consecutively read. this allows users to determine which sectors are in erase and which are not. the status flag is not output from bank (non-busy bank) which doesnt execute embedded algorithm. for example, there is bank (busy bank) which is now executing embedded algorithm. when the read sequence is [1] , [2] , [3] , the dq 6 is toggling in the case of [1] and [3]. in case of [2], the data of memory cells are outputted. in the erase-suspend read mode with the same read sequence, dq 6 will not be toggled in the [1] and [3]. in the erase suspend read mode, dq 2 is toggled in the [1] and [3]. in case of [2], the data of memory cell is outputted.
mbm29pds322te/be 10/11 29 table 9 hardware sequence flags *: successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. reading from non-erase suspend sector address will indicate logic 1 at the dq 2 bit. note 1.dq 0 and dq 1 are reserve pins for future use. 2.dq 4 is fujitsu internal use. status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle * erase suspend- ed mode erase suspend read (erase suspended sector) 1 1 0 0 toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle 0 0 1 * exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspend- ed mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29pds322te/be 10/11 30 dq 7 data polling the device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm an attempt to read device will produce a complement of data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read device will produce true data last written to dq 7 . during the embedded erase algorithm, an attempt to read device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read device will produce a 1 on dq 7 . the flowchart for data polling (dq 7 ) is shown in figure 23. for programming, the data polling is valid after the rising edge of the fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. data polling must be performed at sector address of sectors being erased, not protected sectors. otherwise, the status may be invalid. if a program address falls within a protected sector, data polling on dq 7 is active for approximately 1 m s, then that bank returns to the read mode. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq 7 is active for approximately 400 m s, then the bank returns to read mode. once the embedded algorithm operation is close to completion, the device data pins (dq 7 ) may change asyn- chronously while the output enable (oe ) is asserted low. this means that device is driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if device has completed the embedded algorithm operation and dq 7 has a valid data, data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on the successive read attempts. the data polling feature is active only during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. (see table 9.) see figure 10 for the data polling timing specifications and diagrams. dq 6 toggle bit i the device also features the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the device will results in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during pro- gramming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written is protected, the toggle bit will toggle for about 1 m s and then stop toggling with data unchanged. in erase, device will erase all selected sectors except for ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having data unchanged. either ce or oe toggling will cause dq 6 to toggle. in addition, an erase suspend/resume command will cause dq 6 to toggle. the system can use dq 6 to determine whether a sector is actively erased or is erase-suspended. when a bank is actively erased (that is, the embedded erase algorithm is in progress), dq 6 toggles. when a bank enters the erase suspend mode, dq 6 stops toggling. successive read cycles during erase-suspend-program cause dq 6 to toggle. to operate toggle bit function properly, ce or oe must be high when bank address is changed.
mbm29pds322te/be 10/11 31 see figure 11 for the toggle bit i timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of device under this condition. the ce circuit will partially power down device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in table 8. the dq 5 failure condition may also appear if a user tries to program a non blank location without pre-erase. in this case the device locks out and never complete the embedded algorithm operation. hence, the system never read valid data on dq 7 bit and dq 6 never stop toggling. once device has exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since device was incorrectly used. if this occurs, reset device with command sequence. dq 3 sector erase timer after completion of the initial sector erase command sequence sector erase time-out will begin. dq 3 will remain low until the time-out is completed. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun.if dq 3 is low (0), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see table 9: hardware sequence flags. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the device is in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows: for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also and. furthermore, dq 2 can also be used to determine which sector is being erased. when device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector. to operate toggle bit function properly, ce or oe must be high when bank address is changed.
mbm29pds322te/be 10/11 32 reading toggle bits dq 6 /dq 2 whenever the system initially begins reading toggle bit status, it must read dq 7 to dq 0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq 7 to dq 0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq 5 is high (see the section on dq 5 ). if it is the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq 5 has not gone high. the system may continue to monitor the toggle bit and dq 5 through successive read cycles, deter- mining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (refer to figure 23.) table 10 toggle bit status note successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. reading from non- erase suspend sector address will indicate logic 1 at the dq 2 bit. ry/by ready/busy the device provides a ry/by open-drain output pin as a way to indicate to the host system that embedded algorithms are either in progress or has been completed. if output is low, device is busy with either a program or erase operation. if output is high, device is ready to accept any read/write or erase operation. if the device is placed in an erase suspend mode, ry/by output will be high. during programming, ry/by pin is driven low after the rising edge of the fourth write pulse. during an erase operation, ry/by pin is driven low after the rising edge of the sixth write pulse. ry/by pin will indicate a busy condition during reset pulse. refer to figures 13 and 14 for a detailed timing diagram. ry/by pin is pulled high in standby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle (note) erase-suspend read (erase-suspended sector) 11toggle erase-suspend program dq 7 toggle 1 (note)
mbm29pds322te/be 10/11 33 data protection the device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up device automatically resets internal state machine in read mode. also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. power on/off timing the reset pin must be held low during v cc ramp up to insure that device power up correctly. (refer to figure 5.3.) write pulse glitch protection noise pulses of less than 3 ns (typical) on oe , ce or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
mbm29pds322te/be 10/11 34 n n n n absolute maximum ratings notes: 1.minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods of up to 20 ns. 2.minimum dc input voltage on a 9 , oe and reset pins is C0.5 v. during voltage transitions, a 9 , oe and reset pins may undershoot v ss to C2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in -v cc ) does not exceed +9.0v. maximum dc input voltage on a 9 , oe and reset pins is +11.5 v which may positive overshoot to + 12.5 v for periods of up to 20 ns. 3.minimum dc input voltage on wp /acc pin is C0.5 v. during voltage transitions, wp /acc pin may undershoot v ss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +10.5 v which may positive overshoot to +12.0 v for periods of up to 20ns when vcc is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating ranges operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min. max. storage temperature tstg C55 +125 c ambient temperature with power applied t a C40 +85 c voltage with respect to ground all pins except a 9 , oe , and reset (note 1) v in , v out C0.5 v cc +0.5 v power supply voltage (note 1) v cc C0.5 +3.0 v a 9 , oe , and reset (note 2) v in C0.5 +11.5 v wp /acc (note 3) v acc C0.5 +10.5 v parameter symbol part no. value unit min. max. ambient temperature t a mbm29pds322te/be 10/11 C40 +85 c power supply voltage v cc mbm29pds322te/be 10/11 +1.8 +2.2 v
mbm29pds322te/be 10/11 35 n n n n maximum overshoot / undershoot 0.2 v cc - 0.5 v 20 ns - 2.0 v 20 ns 20 ns figure 1 maximum undershoot waveform v cc + 0.5 v 0.8 v cc v cc + 2.0 v 20 ns 20 ns 20 ns figure 2 maximum overshoot waveform 1 figure 3 maximum overshoot waveform 2 + 11.5 v v cc + 0.5 v + 12.5 v 20 ns 20 ns 20 ns note: this waveform is applied for a 9 , oe and reset
mbm29pds322te/be 10/11 36 n n n n electrical characteristics 1. dc characteristics *1: the i cc current listed includes both the dc operating current and the frequency dependent component. *2: i cc is active while embedded algorithm (program or erase) is in progress. *3: automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: applicable for only v cc applying. *5: embedded algorithm (program or erase) is in progress. (@5 mhz) parameter symbol conditions value unit min. max. input leakage current i li v in = v ss to v cc , v cc = v cc max. C1.0 +1.0 m a output leakage current i lo v out = v ss to v cc , v cc = v cc max. C1.0 +1.0 m a a 9 , oe , reset inputs leakage current i lit v cc = v cc max. a 9 , oe , reset = 11.0 v 35 m a v cc active current * 1 i cc1 ce = v il , oe = v ih , f = 8 mhz 21 ma ce = v il , oe = v ih , f = 1 mhz 3 ma v cc active current * 2 i cc2 ce = v il , oe = v ih 30ma v cc current (standby) i cc3 v cc = v cc max., ce = v cc 0.3 v, reset = v cc 0.3 v 5 m a v cc current (standby, reset) i cc4 v cc = v cc max.,we /acc = v cc 0.3 v, reset = v ss 0.3 v 5 m a v cc current (automatic sleep mode) * 3 i cc5 v cc = v cc max., ce = v ss 0.3 v, reset = v cc 0.3 v v in = v cc 0.3 v or v ss 0.3 v 5 m a v cc active current * 5 (read-while-program) i cc6 ce = v il , oe = v ih 55ma v cc active current * 5 (read-while-erase) i cc7 ce = v il , oe = v ih 55ma v cc active current (erase-suspend-program) i cc8 ce = v il , oe = v ih 35ma v cc active current (intra-page read) i cc9 ce = v il , oe = v ih , f = 20 mhz 5 ma wp /acc accelerated program current i acc v cc = v cc max. wp /acc = v acc max. 20ma input low level v il C0.50.2 v cc v input high level v ih 0.8 v cc v cc +0.3 v voltage for wp /acc sector protection/unprotection and program acceleration * 4 v acc 8.5 12.5 v voltage for autoselect and sector protection (a 9 , oe , reset ) * 4 v id 10.0 11.0 v output low voltage level v ol i ol = 100 m a, v cc = v cc min. 0.1 v output high voltage level v oh i oh = C100 m av cc C0.1 v
mbm29pds322te/be 10/11 37 2. ac characteristics ? read only operations characteristics parameter symbol conditions value(note) unit 10 11 jedec standard min.max.min.max. read cycle time t avav t rc 100 ? 115 ? ns address to output delay t avqv t acc ce = v il oe = v il ? 100 ? 115 ns page read cycle time t prc 45 ? 45 ? ns page address to output delay t pacc ce = v il oe = v il ? 45 ? 45 ns chip enable to output delay t elqv t ce oe = v il ? 100 ? 115 ns output enable to output delay t glqv t oe ? 35 ? 45 ns chip enable to output high-z t ehqz t df ? 30 ? 30 ns output enable to output high-z t ghqz t df ? 30 ? 30 ns output hold time from addresses, ce or oe , whichever occurs first t axqx t oh 0 ? 0 ? ns reset pin low to read mode t ready ? 20 ? 20 m s note: test conditions: output load: c l = 50 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to 2.0 v timing measurement reference level input: 1.0 v output: 1.0 v c l device under test figure 4 test conditions
mbm29pds322te/be 10/11 38 ? write/erase/program operations (continued) parameter symbol value unit 10 11 jedec standard min. typ. max. min. typ. max. write cycle time t avav t wc 100 ?? 115 ?? ns address setup time t avwl t as 0 ?? 0 ?? ns address setup time to oe low during toggle bit polling t aso 15 ?? 15 ?? ns address hold time t wlax t ah 60 ?? 60 ?? ns address hold time from ce or oe high during toggle bit polling t aht 0 ?? 0 ?? ns data setup time t dvwh t ds 60 ?? 60 ?? ns data hold time t whdx t dh 0 ?? 0 ?? ns output enable hold time read t oeh 0 ?? 0 ?? ns toggle and data polling 10 ?? 10 ?? ns ce high during toggle bit polling t ceph 20 ?? 20 ?? ns oe high during toggle bit polling t oeph 20 ?? 20 ?? ns read recover time before write t ghwl t ghwl 0 ?? 0 ?? ns read recover time before write t ghel t ghel 0 ?? 0 ?? ns ce setup time t elwl t cs 0 ?? 0 ?? ns we setup time t wlel t ws 0 ?? 0 ?? ns ce hold time t wheh t ch 0 ?? 0 ?? ns we hold time t ehwh t wh 0 ?? 0 ?? ns write pulse width t wlwh t wp 60 ?? 60 ?? ns ce pulse width t eleh t cp 60 ?? 60 ?? ns write pulse width high t whwl t wph 60 ?? 60 ?? ns ce pulse width high t ehel t cph 60 ?? 60 ?? ns programming operation t whwh1 t whwh1 ? 16 ?? 16 ? s sector erase operation * 1 t whwh2 t whwh2 ? 1 ?? 1 ? s v cc setup time t vcs 50 ?? 50 ?? s rise time to v id * 2 t vidr 500 ?? 500 ?? ns rise time to v acc * 3 t vaccr 500 ?? 500 ?? ns voltage transition time * 2 t vlht 4 ?? 4 ?? s write pulse width * 2 t wpp 100 ?? 100 ?? s oe setup time to we active * 2 t oesp 4 ?? 4 ?? s
mbm29pds322te/be 10/11 39 (continued) *1: this does not include the preprogramming time. *2: this timing is for sector group protection operation. *3: this timing is for accelerated program operation. parameter symbol value unit 10 11 jedec standard min. typ. max. min. typ. max. ce setup time to we active * 2 t csp 44s recover time from ry/by t rb 00ns reset pulse width t rp 500 500 ns reset high level period before read t rh 200 200 ns program/erase valid to ry/by delay t busy 90 90 ns delay time from embedded output enable t eoe 90 115 ns erase time-out time t tow 50 50 s erase suspend transition time t spd 20 20 s power on / off time t ps 100 115 ns
mbm29pds322te/be 10/11 40 n n n n erase and programming performance fbga pin capacitance note: test conditions t a = 25c, f = 1.0 mhz parameter limits unit comments min. typ. max. sector erase time 1 10 s excludes programming time prior to erasure word programming time 16 360 m s excludes system-level overhead chip programming time 100 s excludes system-level overhead program/erase cycle 100,000 cycle parameter symbol condition value unit typ. max. input capacitance c in v in = 0 tbd tbd pf output capacitance c out v out = 0 tbd tbd pf control pin capacitance c in2 v in = 0 tbd tbd pf wp /acc pin capacitance c in3 v in = 0 tbd tbd pf
mbm29pds322te/be 10/11 41 n n n n timing diagram ? key to switching waveforms waveform inputs outputs must be steady may change from h to l may change from l to h "h" or "l": any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance "off" state address addresses stable high-z high-z ce oe we outputs output valid t rc t acc t oe t df t ce t oh t oeh figure 5.1 read operation timing diagram
mbm29pds322te/be 10/11 42 address ce reset outputs high-z outputs valid address stable t rc t acc t rh t rp t rh t ce t oh figure 5.2 hardware reset/read operation timing diagram
mbm29pds322te/be 10/11 43 output high-z a 0 to a 1 a 2 to a 20 ce oe we aa ab ac t rc t acc t ce t oe t oh t oh t oh t df t pacc t pacc t oeh t prc da db dc same page addresses figure 5.3 page read operation timing diagram
mbm29pds322te/be 10/11 44 t ch t cs t wp t whwh1 t wc ce oe t rc address data t ghwl t ce t oe t wph t ds t dh dq 7 pd a0h d out d out we 555h pa pa t oh t as t ah 3rd bus cycle data polling figure 6 alternate we controlled program operation timing diagram notes: 1.pa is address of the memory location to be programmed. 2.pd is data to be programmed at word address. 3.dq 7 is the output of the complement of the data written to the device. 4.d out is the output of the data written to the device. 5.figure indicates last two bus cycles out of four bus cycle sequence.
mbm29pds322te/be 10/11 45 t ws t ghel t wh t cp t whwh1 t wc t ah we oe address data t cph t ds t dh dq 7 pd a0h d out ce 555h pa pa t as 3rd bus cycle data polling figure 7 alternate ce controlled program operation timing diagram notes: 1.pa is address of the memory location to be programmed. 2.pd is data to be programmed at word address. 3.dq 7 is the output of the complement of the data written to the device. 4.d out is the output of the data written to the device. 5.figure indicates last two bus cycles out of four bus cycle sequence.
mbm29pds322te/be 10/11 46 v cc ce oe address data t dh we t wc t as 555h 2aah 555h 555h 2aah sa * t ghwl t wp t cs t ch t ds t vcs t wph t ah aah 10h/ 30h 55h 80h aah 55h figure 8 chip/sector erase operation timing diagram *: sa is the sector address for sector erase. addresses = 555h for chip erase.
mbm29pds322te/be 10/11 47 t oeh t ch t oe t ce t df t busy t eoe t whwh1 or 2 ce dq 7 dq 6 to dq 0 ry/by dq 7 dq 7 = valid data dq 6 to dq 0 = output flag dq 6 to dq 0 valid data oe we high-z high-z data data * figure 9 data polling during embedded algorithm operation timing diagram *: dq 7 = valid data (the device has completed the embedded operation).
mbm29pds322te/be 10/11 48 t oeh ce we oe dq 6 t oe t oes t dh * data (dq 7 to dq 0 ) dq 6 = toggle dq 6 = toggle dq 6 = stop toggle dq 7 = dq 0 data valid figure 10 toggle bit i during embedded algorithm operation timing diagram *: dq 6 stops toggling (the device has completed the embedded operation).
mbm29pds322te/be 10/11 49 figure 11 bank-to-bank read/write timing diagram ce oe address dq t ghwl t df t oe we t wp t oeh t as ba1 read command command read read read ba2 (555h) ba2 (pa) ba2 (pa) ba1 ba1 t ce t dh t df t ds (a0h) (pd) t acc t aht t as t wc t rc t wc t rc t wc t rc t ah t ceph valid output valid input valid output valid input valid output status note: this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1: address of bank 1. ba2: address of bank 2. enter embedded erasing erase suspend erase resume enter erase suspend program erase suspend program erase complete erase erase suspend read erase suspend read erase dq 6 dq 2 we toggle dq 2 and dq 6 with oe figure 12 dq 2 vs. dq 6 note: dq 2 is read from the erase-suspended sector.
mbm29pds322te/be 10/11 50 ce ry/by we the rising edge of the last we signal t busy entire programming or erase operations figure 13 ry/by timing diagram during program/erase operation timing diagram t rp t rb t ready ry/by we reset figure 14 reset , ry/by timing diagram
mbm29pds322te/be 10/11 51 reset data address valid data out t ps t ps v cc valid data in v ih 1.8 v t rh t acc 0 v 1.8 v figure 15 power on / off timing diagram
mbm29pds322te/be 10/11 52 figure 16 sector group protection timing diagram spax: sector group address for initial sector spay: sector group address for next sector t wpp t vlht t vlht t oe t csp t oesp t vcs t vlht t vlht a 20 , a 19 , a 18 a 17 , a 16 , a 15 a 14 , a 13 , a 12 a 6 , a 3 , a 2 , a 0 a 1 a 9 v cc oe v id v ih v id v ih we ce data spax 01h spay
mbm29pds322te/be 10/11 53 unprotection period t vlht t vlht t vcs t vlht t vidr program or erase command sequence v cc v id v ih we ry/by ce reset figure 17 temporary sector group unprotection timing diagram
mbm29pds322te/be 10/11 54 v cc we oe ce reset t wc t wc t vlht t vidr t vcs time-out spax spax spay t wp t oe 60h 01h 40h 60h 60h data address a 6 , a 3 , a 2 , a 0 a 1 figure 18 extended sector group protection timing diagram spax: sector group address to be protected spay: next sector group address to be protected time-out: time-out window = 250 m s (min.)
mbm29pds322te/be 10/11 55 wp/acc v acc v ih we ce ry/by t vlht program or erease command sequence t vlht v cc t vcs t vaccr t vlht acceleration period figure 19 accelerated program timing diagram
mbm29pds322te/be 10/11 56 n n n n flow charts 555h/aah 555h/a0h 2aah/55h program address/program data programming completed last address ? increment address verify data ? data polling program command sequence (address/command) : write program command sequence (see below) start no no yes yes embedded program algorithm in program figure 20 embedded program tm algorithm embedded algorithm
mbm29pds322te/be 10/11 57 figure 21 embedded erase tm algorithm embedded algorithm 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah sector address /30h sector address /30h sector address /30h 2aah/55h erasure completed data = ffh ? data polling write erase command sequence (see below) start no yes embedded erase algorithm in progress chip erase command sequence (address/command) : individual sector/multiple sector erase command sequence (address/command) : additional sector erase commands are optional.
mbm29pds322te/be 10/11 58 dq 7 = data? dq 5 = 1? fail pass dq 7 = data? * read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va start no no no yes yes yes figure 22 data polling algorithm *: dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va=address for programming =any of the sector address within the sector being erased during sector erase or multiple sector erases operation =any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation.
mbm29pds322te/be 10/11 59 toggle bit = toggle? dq 5 = 1? toggle bit = toggle? read dq 7 to dq 0 addr. = va read dq 7 to dq 0 addr. = va read dq 7 to dq 0 twice addr. = va start no no no yes yes yes *1 *1, 2 fail pass figure 23 toggle bit algorithm va=bank address being executed embedded algorithm. *1: read toggle bit twice to determine whether or not it is toggling. *2: recheck toggle bit because it may stop toggling as dq 5 changes to 1.
mbm29pds322te/be 10/11 60 start no no no yes yes yes data = 01h? device failed plscnt = 25? plscnt = 1 remove v id from a 9 write reset command remove v id from a 9 write reset command sector group protection completed protect another sector group? increment plscnt read from sector group addr. = spa, a 1 = v ih a 6 = a 3 = a 2 = a 0 = v il setup sector group addr. a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 oe = v id , a 9 = v id ce = v il , reset = v ih a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih activate we pulse time out 100 m s we = v ih , ce = oe = v il (a 9 should remain v id ) () () * figure 24 sector group protection algorithm
mbm29pds322te/be 10/11 61 start perform erase or program operations reset = v id *1 reset = v ih temporary sector group unprotection completed *2 figure 25 temporary sector group unprotection algorithm *1: all protected sector groups are unprotected. *2: all previously protected sector groups are protected once again.
mbm29pds322te/be 10/11 62 figure 26 extended sector group protection algorithm start no yes yes data = 01h? plscnt = 1 no no yes device failed plscnt = 25? remove v id from reset write reset command sector protection completed protect other sector group? increment plscnt read from sector group address (addr. = spa, a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih ) remove v id from reset write reset command time out 250 m s reset = v id wait to 4 m s no yes setup next sector address device is operating in temporary sector group unprotection mode to protect secter group write 60h to secter address (a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih ) to verify sector group protection write 40h to secter address (a 6 = a 3 = a 2 = a 0 = v il , a 1 = v ih ) to setup sector group protection write xxxh/60h extended sector group protection entry?
mbm29pds322te/be 10/11 63 figure 27 embedded program tm algorithm for fast mode fast mode algorithm 555h/aah 555h/20h xxxh/90h xxxh/f0h xxxh/a0h 2aah/55h program address/program data programming completed last address? increment address verify data? data polling start no no yes yes set fast mode in fast program reset fast mode
mbm29pds322te/be 10/11 64 n n n n ordering information standard products fujitsu standard products are available in several packages. the order number is formed by a combination of: mbm29pds322 t e 10 pbt device number/description mbm29pds322 32 mega-bit (2 m 16-bit) cmos flash memory 1.8 v-only read, program, and erase package type pbt =63-ball fine pitch ball grid array package (fbga) speed option see product selector guide device revision boot code sector architecture t = top sector b = bottom sector valid combinations mbm29pds322te/be 10 11 pbt valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations.
mbm29pds322te/be 10/11 65 n n n n package dimension 63-pin plastic fbga (bga-63p-m01) dimensions in mm (inches). c 1999 fujitsu limited b63001s-1c-1 11.00?.10(.433?004) .041 ?004 +.006 ?.10 +0.15 1.05 (mounting height) 1 2 3 4 5 6 7 8 a b c d e f g h 0.80(.031)typ (5.60(.220)) (5.60(.220)) index ball m 0.08(.003) 0.10(.004) index area 7.00?.10 (.276?004) (7.20(.283)) j k (63-0.18?002) 63-0.45?.05 ml (8.80(.346)) (4.00(.157)) 0.38?.10 (.015?004) (stand off)
mbm29pds322te/be 10/11 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0101 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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